The disadvantage of this circuit arrangement is that harmonics are produced in the network by the half-bridge circuit and the DC link capacitor required with such switched-mode power supplies. In accordance with IEC Publication 555-2, this line current harmonic content must, from 1996, fulfill Class C of the regulations for ballasts or converters with a power consumption of greater than 25 W, and, from 1998, Class D of the regulations for compact lamps, ballasts and adapters with a power consumption of less than or equal to 25 W.
Since the magnitude of the DC link capacitor is proportional to the power consumption of the lamp, ballasts for lamps of greater than 25 W require DC link capacitors with relatively high capacitances. However, the latter entail a high harmonic content, with the result that these lamps require active harmonic filter circuits in the form of complicated pumping circuits with capacitors and diodes in order to be able to fulfill the IEC regulations of Class C. Such a circuit arrangement is described, for example, in DE-A 36 23 749. Moreover, these active circuits entail additional radio interference which can only be suppressed with a high outlay on components.
It is the object of the invention to create a circuit arrangement for operating low-power low-pressure discharge lamps, that is to say those of less than or equal to 25 W, which keeps the line current harmonic content below the maximum values laid down in Class D of the IEC publications. The circuits outlay required for this purpose should be as low as possible and be capable of being implemented cost-effectively.
DE 44 30 397 has disclosed a circuit arrangement which keeps the harmonic content below the maximum value laid down in Class D of the IEC publications, and requires three capacitors (with the DC link capacitor) and two diodes to create a low-capacitance DC link.